Galena

Capabilities

FPGA Engineering

RTL design in VHDL and Verilog across FPGA platforms. Timing closure, synthesis optimisation, AXI-Stream interfaces, hardware verification and validation. ASIC synthesis and PPA analysis via open-source flows including OpenLane.

Deterministic & Real-Time Systems

Hardware architectures where timing predictability is a design constraint. Fixed-latency pipelines, cycle-accurate execution, and buffer-free designs for safety-critical and latency-sensitive applications.

High-Performance Computing

High-throughput hardware architectures for data-intensive applications. Line-rate packet processing, hardware accelerators, and pipelined FPGA designs optimised for sustained throughput at scale.

ISA Design & Computer Architecture

Custom RISC-V ISA extensions for resource-constrained environments. Logic-only arithmetic acceleration achieving order-of-magnitude speedups with zero DSP utilisation. Edge ML inference on legacy and low-cost FPGA fabrics.

Hardware Security

EM side-channel characterisation of embedded and specialist hardware. Physical trace acquisition and ML-based classification. Research into capability-based security enforcement mechanisms at the hardware level.

Defence Engineering

Engineering experience across operational defence environments. Familiarity with the constraints, standards, and disciplines of defence-grade engineering.

Ongoing Research

EM Side-Channel Analysis of CHERIoT-Ibex

EM side-channel characterisation of the CHERIoT-Ibex processor on the Sonata FPGA platform. Near-field trace acquisition via RTL-SDR, targeting capability check pass/fail leakage. ML-based classification over labelled trace sets. No prior published EM analysis of CHERI capability hardware exists in the literature.

CHERI Capability Hardware on a Minimal RISC-V Soft Core

Implementation of CHERI capability checking hardware on a custom RV32IM soft core. Cycle-accurate measurement of capability enforcement overhead — area, timing, and determinism — on a minimal FPGA platform. Assessing whether capability validation latency is sufficiently predictable for real-time embedded deployment.

EM Side-Channel Characterisation of Custom RISC-V ISA Extensions

Investigation of electromagnetic leakage from custom instructions implemented in reconfigurable logic. Examining whether distinct logic structures produce distinguishable EM signatures, and the security implications for FPGA deployments using custom ISA extensions. Builds on a verified RV32IM soft core platform with established bare-metal benchmarking infrastructure.

Publications

IEEE COOL Chips 29 — Tokyo, April 2026

Zero-Jitter Packet Parsing: A Deterministic Buffer-Free FPGA Architecture for Fixed-Latency Flow Extraction

A buffer-free hardware architecture for extracting L2–L4 flow telemetry at line rate. Fixed 11-cycle metadata extraction latency with zero observed variance under randomised traffic, implemented on Xilinx Zynq-7020.

Presented at the IEEE Symposium on Low-Power and High-Speed Chips and Systems, Tokyo.

Specialist FPGA engineering and hardware security research for defence and technology organisations.